Flip-flop circuits are used in semiconductor devices to maintain a binary state until directed by an input signal to switch states. A variation of the basic flip-flop circuit, the docked flip-flop circuit responds to input levels in response to a clock signal. Used in this manner, the clocked flip-flop circuit acts as a sampling device which only reads the information off of its input line when directed to do so by the clocking circuit. After reading the information, the circuit stores the information and outputs it on the output line. In all other instances of time, the circuit will not respond to input signals and will remain unchanged during variations of signal states on the input line.
Despite their usefulness, typical flip-flops have many shortcomings. One such typical flip-flop is the master-slave flip-flop. The master-slave flip-flop comprises two latches, a master latch and a slave latch. With the two latches, the master-slave flip-flop can be designed to be an edge triggered device, either positive edge triggered or negative edge triggered. The data signal provided to a master-slave flip-flop is transmitted through the master latch and through the slave latch. The master latch and the slave latch are coupled to a clock signal. The master latch stores the data signal when the clock signal is in a first signal state and the slave latch stores the signal from the master latch when the clock signal is in a second signal state. In this manner, the master-slave flip-flop samples and holds a data signal during a positive clock edge or a negative clock edge.
Although relatively slow, the prior master-slave flip-flops satisfied existing design requirements. In processor devices, master-slave flip-flops are used in registers. The speed of the registers in a processor along with the speed of associated combinatorial logic in the processor are both factors which determine the clock frequency at which the processor can operate at and thus, determines the performance capability of the processor. In prior processors, the combinatorial logic consumed the majority of clock cycle time. However, with newer architectures, combinatorial logic used in processors have experienced improvements in speed. As such, the percentage of the clock period attributable to combinatorial logic has decreased and the percentage of the clock period attributable to flip-flops has increased. Thus, because flip-flop delays account for a larger percentage of the clock period, it has become increasingly important to enhance the speed of flip-flops to enhance the overall performance of processors.
In addition, the prior master-slave flip-flop also consumed a relatively large amount of power. In the past, VLSI (Very Large Scale Integration) circuits (e.g. microprocessors) were relatively simple with fewer storage elements. However, as microprocessors and other VLSI circuits increase in complexity, the number of storage elements increase proportionately and thus, the number of flip-flops used also increases. With the increase in the number of flip-flops, the proportion of power consumption attributable to clocking of flip-flops also increases. As such, it has become increasingly important to reduce the power consumption of the flip-flops used in VLSI circuits such as a microprocessor. In this manner, power consumption of VLSI circuits can be reduced.
Thus, a flip-flop circuit is needed which has improved performance through greater speed. What is also needed is a flip-flop circuit that has reduced power consumption.